1. Field of the Invention
The present invention relates to a clock reproduction circuit and, more particularly, to a clock reproduction circuit that reproduces a clock signal from an input serial data signal including multi-valued data.
2. Description of the Related Art
There is known a signal transmission system that uses multi-valued data in place of binary data, in a serial data signal to be transmitted. Patent Publication JP-05-236043A describes a clock reproduction circuit used in a multi-valued data receiving circuit. In general, a clock reproduction circuit installed in a receiving circuit detects the falling edge and the rising edge of a transmitted serial data signal and sets the clock pulse of the reproduced clock signal between the rising edge and the falling edge or between the falling edge and the rising edge.
The clock reproduction circuit described in JP-05-236043A detects a timing at which multi-valued data crosses a plurality of reference voltage levels and compares the phase between the detected timing and the output clock signal of the clock reproduction circuit, to thereby output a phase error signal in proportion to the result of the phase comparison. Based on the magnitude of the phase error signal, the phase and frequency of the reproduced clock are controlled. The clock reproduction circuit adopts the method described above to allow the reproduced clock signal in the receiving circuit to be pulled in synchrony with the transmitted data signal at a high speed.
In the case where multi-valued data is used in a high-speed signal transmission system, a transmission data signal assumes a plurality of levels of signal amplitude corresponding to the data values. Accordingly, the timing at which an input signal crosses a plurality of reference voltages in the receiving circuit varies depending on the value of the data transmitted. Therefore, if a technique is used in which the rising and falling edges of the transmitted signal are detected and the clock pulse of the reproduced clock signal is set between the rising (falling) edge and the falling (rising) edge, the center of the clock pulse of the reproduced clock signal is deviated from the center of the signal waveform depending on the level of the data value, with the result that jitter is generated in the reproduced clock signal. If the center of the clock pulse of the reproduced clock signal is deviated from the center of the reproduced data, the time margin for identifying the reproduced data is reduced. In particular, the problem of the insufficient time margin will be critical in a higher-speed signal transmission system.